1. Field of the Invention
The present invention relates the manufacture of semiconductor devices, and more particular, to improving grain growth and reducing voids during such manufacturing.
2. Related Art
Integrated circuits fabricated on semiconductor substrates for very and ultra large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next.
As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers need to be as small as possible. One way to reduce the size of interconnection lines and vias is to use copper (Cu) as the interconnect material instead of conventionally used materials such as aluminum (Al). Because copper has lower resistivities and significantly higher electromigration resistance as compared to aluminum, copper advantageously enables higher current densities experienced at high levels of integration and increased device speed at higher frequencies. Thus, major integrated circuit manufacturers are transitioning from aluminum-based metallization technology to dual damascene copper technology. Copper interconnect lines can also be made thinner than aluminum lines, which reduces crosstalk between the lines.
However, as devices get smaller and smaller, the copper lines become increasingly thinner and narrower. Due to the characteristics of copper, as the copper lines become thinner and narrower, the resistivity of the copper increases and approaches that of aluminum. One way to reduce the resistivity is to self-anneal the copper, i.e., the copper undergoes a re-crystallization at room temperature. This results in a reduction in resistivity and a physical change in the copper structure. Sheet resistance, in the past, has been reduced by annealing at room temperature for a longer time.
However, copper self-anneal does not grow larger grains. Larger grain sizes are advantageous for reducing adverse effects from the change in the copper microstructure. The adverse effects include a higher resistance in the lines with very small dimension due to electron scattering from grain boundaries, defects, and surfaces. One method to grow larger grains, while still reducing sheet resistance, is to anneal the copper at temperatures higher than room temperature, e.g., greater than 100° C. This results in growing larger grains, along with clear grain boundaries. This method may be suitable for annealing blanket copper film, but with thin narrow copper wires (e.g., 500 or 1000 angstroms wide), annealing at higher temperatures can become problematic since the grain size approaches the size of the copper wire. Growing grains in small wires is also difficult due to the amount of material available for the grain growth. Grain growth also results in small micro-voids between the grains. Consequently, as grain boundaries are grown, the number of grains and the curvature of the grain boundaries decrease.
During anneal process steps, grain growth of the copper films also creates stresses that can damage or destroy the thin film. The stresses lead to warping and bowing and ultimately to film cracking which undermines desired low resistivity of the copper. Micro-voids are also formed during the copper deposition. Micro-voids can cause reliability problems and other associated adverse effects with the resulting copper film. Self-annealing does not remove the micro-voids.
Therefore, there is a need for forming copper films that overcome the disadvantages of conventional methods discussed above.